1. Field of the Invention
The present invention relates to test features built-in to a silicon device for testing high-speed serial links and, more particularly, to establish a differential signal (voltage) margin and time margin in a serial link to ensure a more robust link.
2. Background Art
When two components in a processor-based communications systems such as HyperTransport™ bus architectures are connected via a high-speed differential link, it is difficult to determine an operating margin of the link. As used herein the “margin” is an additional amount of time and/or voltage provided before the link fails. When a system is turned on and is operational, one does not know how much operating margin exists as a function, for example, of device aging, temperature, voltage, etc. Voltage may be manifested as noise or differences in phase may be manifested as jitter. Thus, it is difficult to establish the effective bit error rate of the link. Systems should be configured such that there is a low probability of errors occurring on the link. Since a portion of the jitter is random in nature, the only way to be certain of low error probability, without measuring the error rate, is to wait a very long time between failures. This is simply not practical in testing or characterization of new silicon.